1. Technical Field
The present invention relates to a semiconductor device having a trench gate IGBT structure.
2. Background Art
As power converters continue to consume less power, there are increasing expectations for power devices, which play a central role in the power converters, to also consume less power. Among these power devices, voltage-driven insulated gate bipolar transistors (IGBTs) are being used. These IGBTs are capable of realizing low ON-voltages due to conductivity modulation and of easily controlling current by applying voltage to an insulated gate. Planar gate IGBTs, trench gate IGBTs, and the like are known as types of IGBTs, for example.
The planar gate IGBTs have a metal oxide semiconductor (MOS) gate structure in which an oxide film and a gate electrode are provided on a flat part of the front surface-side of a silicon substrate. The trench gate IGBTs have a MOS gate structure in which an oxide film and gate electrodes (hereafter referred to as trench gates) embedded in polysilicon are provided within trenches formed on the front surface-side of a silicon substrate. The trench gate IGBTs have channels formed along both lateral walls of the trenches, thus allowing greater channel density per unit area and lower ON-voltage than those of the planar gate IGBTs, which have channels formed along the front surface of the substrate. Thus, recently, the fields in which trench gate IGBTs can be applied have been increasing.
Here, the main points of conventional trench gate IGBT technology are described using a trench gate IGBT according to Patent Document 1 below as an example.
FIG. 4 schematically shows a cross section cut in the direction (a lateral direction) that trenches of the trench gate IGBT, which is provided with floating p regions, are arranged. As shown in the same figure, a p− layer 4 is provided on one surface layer of a silicon substrate that is provided with an n drift layer 1. An n+ buffer layer 3 is provided on the other surface layer of the silicon substrate. A p+ collector layer 2 is provided under the n+ buffer layer 3. Hereafter, the side that is provided with the p− layer 4 is defined as the front surface of the silicon substrate, and the side that is provided with the p+ collector layer 2 is defined as the back surface of the silicon substrate. The trench gate IGBT is provided with a plurality of trenches 6 that penetrate from the front surface-side of the silicon substrate, through the p− layer 4, reaching then drift layer 1 in the depth direction. The p− layer 4 is segmented into first p base regions 12 and floating p regions 13 by the trenches 6. The first p base regions 12 and the floating p regions 13 are repeatedly disposed in an alternating fashion in the lateral direction that the trenches 6 are arranged, for example, and extend as straight lines that are parallel to the trenches 6 in a longitudinal direction orthogonal to the lateral direction. Selectively provided inside of the first p base regions 12 are n+ emitter regions 5. Furthermore, selectively provided inside of the first p base regions 12 and adjacent to the n+ emitter regions 5 are second p base regions 11. Portions of the first p base regions 12 along the lateral walls of the trenches 6 have n-type inversion layers formed thereon. The n-type inversion layers become paths for the main current during the ON state.
An emitter electrode 10 is conductively connected to the second p base regions 11 and the n+ emitter regions 5 via contact holes provided in an interlayer insulating film 9. A collector electrode 14 is conductively connected to the p+ collector layer 2 at the back surface-side of the silicon substrate. Gate electrodes 8 are provided inside the trenches 6 with gate insulating films 7 interposed therebetween.
Next is a description of the operation of the trench gate IGBT during turn-ON, which is when the trench gate IGBT transitions from the OFF state to the ON state. Normally, the emitter electrode 10 is connected to ground or has a negative voltage applied thereto. The collector electrode 14 has a positive voltage applied thereto. In this manner, when a voltage applied to the gate electrodes 8 is lower than the threshold value, even when a voltage that is higher than the voltage at the emitter electrode 10 is applied to the collector electrode 14, current does not flow between the emitter electrode 10 and the collector electrode 14, because the p-n junction between the first p base region 12 and then drift layer 1 is reverse biased. That is, the IGBT maintains the OFF state. When a voltage that exceeds the threshold value is applied to the gate electrode 8, electric charge begins to accumulate in the gate electrode 8, and at the same time, channel regions that have inverted into n-type regions are formed on the surface layers of the first p base regions 12 in contact with the gate insulating films 7 and are facing the gate electrodes 8. Thus, electrons emitted from the emitter electrode 10 travel through n-type regions composed of the n+ emitter regions 5 and the channel regions and are injected into then drift layer 1. The injection of the electrons into the n− drift layer 1 causes the p-n junction between the p+ collector region 2 and then drift layer 1 to become forward biased and injects positive holes into the n− drift layer 1 from the collector electrode 14, thus causing a current to flow between the emitter electrode 10 and the collector electrode 14 and the IGBT to enter the ON state. The ON-voltage is the voltage drop between the emitter electrode 10 and the collector electrode 14 in the ON state.
In this IGBT, the positive holes injected into then drift layer 1 from the collector side do not easily travel to the emitter electrode 10 when the IGBT is in the ON state, because of the floating p regions 13, which are electrically insulated from the emitter electrode 10 by the interlayer insulating films 9. Thus, the positive holes accumulate in the floating p regions 13, and the carrier concentration distribution of then drift layer 1 is increased to a level close to the carrier concentration distribution of a diode, causing the ON-voltage to lower.
However, in this trench gate IGBT, which is provided with the floating p regions 13, a displacement current corresponding to the gate-collector capacitance flows through the gate electrodes 8 into the floating p regions 13 during turn-ON, because the floating p regions 13 and the gate electrodes 8 face each other across the gate insulating films 7, which are provided on the lateral walls of the trenches interposed therebetween. This displacement current charges the input capacitance, and the gate voltage increases, thus creating a problem in which the rate of change in the collector current during turn-ON becomes large and the controllability of the switching speed deteriorates.
In the trench gate IGBTs according to Patent Documents 2 and 3 below, the above problem is dealt with by providing shield electrodes on surfaces in contact with the floating p regions 13 and/or lateral surfaces in contact with the trenches 6.